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Flash-Write Algorithm
PRELIMINARY
3-17
Algorithm Implementations and Software Considerations
PRELIMINARY
The CPU frequency range for the application is an important consideration for
the depletion test, as well as for the program and erase operations. Because
of the actual implementation of the flash memory circuitry, a bit in depletion
mode is most easily detected at low frequency. Accordingly, if the application
requires a variable CPU clock rate, the depletion test should be performed at
the lowest frequency in the range. Only the read portion of the depletion test
must be performed at the lower frequency, because it is the read that is used
to detect depletion. The effective duration of the read operation can be ex-
tended by sequentially executing multiple reads on the same location. Be-
cause the same address is selected the entire time and internal control signals
are maintained between reads, the final read is equivalent to a slow read. For
example, if the DSP core is executing the programming algorithm at a
CLKOUT rate of 20 MHz (50 ns), sequentially reading a location three times
is equivalent to reading it once at 6.67 MHz (150 ns). The erase and flash-write
algorithm implementations given in Appendix A use three reads to check for
depletion.