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Operating
Prhcip/es
2.3.2.6
DMA
Controller
Data from the host computer is received automatically by the
/STB
signal via the external
Centronics interface. The data is input into the input buffer on the D-RAM
(IC5).
At this time,
E05A96
detects the rising edge of the external
/STB
signal and outputs the
/ST’BDMA
(strobe
DMA
request) signal to the CPU. When the CPU detects this signal, the
DMA
controller in the CPU
sends a bus request to the bus controller in the CPU, and then the CPU releases the bus line. Due to
this, the external data is transported into the memory, bypassing the CPU.
E05A96
(IC2)
CPU H8 (ICI)
STB
ACK
BUSY
*
STBDMA
132 9
➤
DREQ1
, ---------------
.--------------,
4
:
DMAC
\
:
BAC
;
4
‘. . .
.
. . .
.
DREQ2
BAREQ
Figure 2-26.
DMA
Controller Operation
Memory
Rev. A
2-21