Filter
Top Products
Opwating
Pr’inc@es
Sty/w
Color
Servke
Manual
2.3.2.7
D-RAM Refreshment Controller
The
H8 CPU is eauimxd with a the refresh controller into the internal
mntroller.
This
CPU can
contact the 16-bit
ien’~
IC5
D-RAM which is a 2
CAS
type. The fallowing table lists the
method between the H8 CPU and the 2
CAS
BRAM.
Table 2-10. Junction Method
(CPU-2CAS
DRAM)
CPU
2
CAS
D-RAM
HWR
UCAS
im
LCAS
CS3
m
m
m
*
The
method of the D-RAM
reikeshment
is only
following figure shows the timing of each cycle.
UCAS
LCAS
AS
L ,
I
I
Read Cycle
I
used to the
CAS
befbre
RAS
cycle method. The
I
*-””--”
1
Write Cycle
. . . . . . . . . . . . . . . . . . . . . .
I
I
1
J
(Read
/
Write Cycle)
Figure 2-27. D-RAM Cycle Timings
(Refresh Cycle)
CPU H8 (ICI)
D-RAM
(IC5)
79
28
“
“
HWR 80
~
OCAS
LWR ,
~,
&
14F
LCAS
=3
78
RAS
13b
—
RD
27+
M
+
OE
I
J
1
J
Figure 2-28. Junction Method (CPU-DRAM)
2-22
Rev. A