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98 EPSON S1C63558 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
FER: Serial interface (1) framing error flag (FF73H•D2)
FERS: Serial interface (2) framing error flag (FF5BH•D2)
Indicates the generation of a framing error.
When "1" is read: Error
When "0" is read: No error
When "1" is written: Reset to "0"
When "0" is written: Invalid
FER/FERS is an error flag that indicates the generation of a framing error and becomes "1" when an error
has been generated.
When the stop bit for the receiving in the asynchronous mode has become "0", a framing error is gener-
ated.
FER/FERS is reset to "0" by writing "1".
FER/FERS is set to "0" at initial reset or when RXEN/RXENS is set to "0".
EISRC, EISTR, EISER: Serial interface (1) interrupt mask registers (FFE3H•D0, D1, D2)
EISRCS, EISTRS, EISERS: Serial interface (2) interrupt mask registers (FFE8H•D0, D1, D2)
Enables or disables the generation of an interrupt for the CPU.
When "1" is written: Enabled
When "0" is written: Disabled
Reading: Valid
EISRC/EISRCS, EISTR/EISTRS and EISER/EISERS are interrupt mask registers that respectively corre-
spond to the interrupt factors for receivie completion, transmit completion and receive error. Interrupts set
to "1" are enabled and interrupts set to "0" are disabled.
At initial reset, these registers are set to "0".
ISRC, ISTR, ISER: Serial interface (1) interrupt factor flags (FFF3H•D0, D1, D2)
ISRCS, ISTRS, ISERS: Serial interface (2) interrupt factor flags (FFF8H•D0, D1, D2)
Indicates the serial interface interrupt generation status.
When "1" is read: Interrupt has occurred
When "0" is read: Interrupt has not occurred
When "1" is written: Flag is reset
When "0" is written: Invalid
ISRC/ISRCS, ISTR/ISTRS and ISER/ISERS are interrupt factor flags that respectively correspond to the
interrupts for
receivie completion, transmit completion and receive error,
and are set to "1" by generation of
each factor.
Transmit completion interrupt factor is generated at the point where the data transmition of the shift
register has been completed.
Receive completion interrupt factor is generated at the point where the received data has been transferred
into the receive data buffer.
Receive error interrupt factor is generated when a parity error, framing error or overrun error has been
detected during data receiving.
When set in this manner, if the corresponding interrupt enable mask is set to "1" and
the CPU is set to
interrupt enabled status (I flag = "1")
, an interrupt will be generated to the CPU.
Regardless of the interrupt mask register setting, the interrupt factor flag will be set to "1" by the occurrence
of an interrupt generation condition.
The interrupt factor flag is reset to "0" by writing "1".
After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag = "1") is
set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset
(write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt
enabled state.
At initial reset, these flags are set to "0".