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146 EPSON S1C63558 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
Fig. 4.16.1 Configuration of the interrupt circuit
K10
KCP10
SIK10
K11
KCP11
SIK11
K12
KCP12
SIK12
K13
KCP13
SIK13
IK1
EIK1
IT3
EIT3
IT2
EIT2
IT1
EIT1
IT0
EIT0
ISW1
EISW1
ISW10
EISW10
IPT0
EIPT0
IPT1
EIPT1
ISERS
EISERS
ISRCS
EISRCS
ISTRS
EISTRS
ISER
EISER
ISRC
EISRC
ISTR
EISTR
Interrupt
vector
generation
circuit
Program
counter
(low-order 4 bits)
INT
Interrupt request
NMI request
Watchdog timer
Interrupt factor flag
Interrupt mask register
Input comparison register
Interrupt selection register
Interrupt flag
ID
EID
ICDET
EICDET
IRDET
EIRDET
K00
KCP00
SIK00
K01
KCP01
SIK01
K02
KCP02
SIK02
K03
KCP03
SIK03
IK0
EIK0