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82575 Ethernet Controller Design Guide
18
Figure 5. Proper power sequencing for 82575 Ethernet Controller
Figure 6. Power On Flowchart
In addition, the following limitations exist:
W
Y
Y
Y
Y
Vcc power on
LAN_PWR_GOOD reset
Load EEPROM
Initialize FW
Configure MAC and PHY
Initialize RMII link
PE_RST_n reset
Initialize PCI-E
Run Manageability FW
Dr mode
Platform
powered
?
No
Yes
D0 mode
“veto” bit
on?
Reset MAC
Load EEPROM
no
yes
Reset PHY
HW operation
FW operation