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82575 Ethernet Controller Design Guide
24
The table below summarizes link speed as function of power management state, link
speed control, and gigabit speed enabling:
3.6.5 Link Energy Detect
The PHY de-asserts the Link Energy Detect Bit (PHYREG 25.4) whenever energy is not
detected on the link. This bit provides an indication of a cable becoming plugged or
unplugged.
This bit is valid only if auto-negotiation is enabled.
In order to correctly deduce that there is no energy, this bit must read as zero for three
consecutive reads each second.
3.6.6 Polarity Correction
The PHY automatically detects and corrects for the condition where the receive signal
(MDI_PLUS_0/MDI_MINUS_0) is inverted. Reversed polarity is detected if eight
inverted link pulses, or four inverted end-of-frame markers, are received consecutively.
If link pulses or data are not received for 96-130 ms, the polarity state is reset to a
non-inverted state.
Automatic polarity correction may be disabled by setting Bit PHYREG.27.5
Gigabit disable bits
Power
Management
State
Low Power
Link Up
(reg 25.1
& 2)
Disable
1000 (reg
25.6)
Disable
1000 in
non-D0a
(reg 25.3)
PHY speed
negotiation
D0a
0
0
X
PHY negotiates to
highest speed
advertised ("normal
operation")
1
PHY negotiates to
highest speed
advertised ("normal
operation"), excluding
1000
1
0
X
PHY goes through Low
Power Link Up (LPLU)
procedure, starting
with advertised values
1
PHY goes through
LPLU procedure,
starting with
advertised values.
Does not advertise
1000
Non-D0a
0
00
PHY negotiates to
highest speed
advertised
0 1 PHY negotiates to
highest speed
advertised, excluding
1000
1X
1
00
PHY goes through
LPLU procedure,
starting at 10
01
PHY goes through
LPLU procedure,
starting at 10. Does
not advertise 1000