Intel 317698-001 Switch User Manual


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41
82575 Ethernet Controller Design Guide
Figure 13. Layout for Integrated Magnetics
Figure 14. Layout for Discrete Magnetics
Termination resistors
placed within 250 mils
of silicon
TVS Diodes for improved
CDE Protection
GND plane cut for
High POT isolation
Termination resistors
placed within 250 mils
of the silicon
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