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82575 Ethernet Controller Design Guide
1.0 Introduction
The Intel
®
82575 Ethernet Controller is a single, compact component that offers two
fully-integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY)
ports. This device uses the PCI Express* (PCIe) architecture (Rev. 1.1RD). The 82575
enables two-port implementation in a relatively small area and can be used for server
and workstation network designs with critical space constraints.
The 82575 provides:
• a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and
10BASE-T applications (802.3, 802.3u, and 802.3ab).
• a Serializer-Deserializer (SERDES) to support 1000Base-SX/LX (optical fiber) and
Gigabit backplane applications. Information concerning SERDES can be found in the
82575 Ethernet Controller SERDES Application Note.
• SGMII for SFP/external PHY
• management of MAC and PHY Ethernet layer functions
• management of PCI Express packet traffic across its transaction, link, and physical/
logical layers.
• I/O Acceleration Technologies (I/OAT2). to accelerate the data transactions by
hardware means optimizing the TCP flow and reducing the load on the CPU.
In addition, the 82575’s on-board System Management Bus (SMB) ports enable
network manageability implementations required by information technology personnel
for remote control and alerting via the LAN. With SMB, management packets can be
routed to or from a management processor. The SMB ports enable industry standards,
such as Intelligent Platform Management Interface (IPMI) and Alert Standard Forum
(ASF) 2.0, to be implemented using the 82575. In addition, on-chip ASF 2.0 circuitry
provides alerting and remote control capabilities with standardized interfaces. The
82575 Ethernet Controller contains a dedicated microcontroller for manageability with
with NC-SI and DMTF support.
The 82575 with PCIe architecture is designed for high-performance and low-host-
memory access latency. The device connects directly to a system Memory Control Hub
(MCH) or I/O Controller Hub (ICH) using one, two, or four PCI Express lanes.
Wide internal data paths eliminate performance bottlenecks by efficiently handling
large address and data words. Combining a parallel and pipelined logic architecture
optimized for ethernet and independent transmit and receive queues, the 82575
efficiently handles packets with minimum latency. The 82575 includes advanced
interrupt handling features. It uses efficient ring buffer descriptor data structures, with
up to 64 packet descriptors cached on chip. A large 48 KByte on-chip packet buffer
maintains superior performance. In addition, using hardware acceleration, the
controller offloads tasks from the host, such as TCP/UDP/IP checksum calculations and
TCP segmentation.
The 82575 is packaged in 25mm x 25mm, 576-ball grid array.
1.1 Scope
This application note contains Ethernet design guidelines applicable to LOM designs
based on PCI Express-supported chipsets.