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STP2002QFP
Sun Microelectronics
Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP
slave accesses from SBus. The physical address is decoded to select a target
CE to respond to the access. A physical address that cannot be resolved to the
selection of any channel engine will cause SBus Adapter to return Error Ack.
The access size is decoded to Error Ack 64-bit transfer mode or burst transfer
that is not supported by FEPS.
2.3 Theory of Operation
2.3.1 Master Operations
All master operations are originated from the channel engines. The operations
start when one or more bus requests are asserted on the channel engine inter-
face.
2.3.1.1 DVMA Write
DVMA write cycle starts when the channel engine with highest priority as-
serts BR signal on CEI with RD (bit[63] of CE_DOUT signal) signal de-as-
serted. The arbiter inside SBA asserts grant signal (BG) to the requesting CE
and kick off the CEI write state machine. CEI write state machine first latches
the DVMA address, transfer size and channel ID from the requesting CE and
then begin to move data from CEI and write them to the current DVMA data
write buffer. When the whole burst of write data are written to the write buff-
er, the CEI state machine places a write request into the request command
queue of the SBus Master Port State machine and, at the mean time, it release
the arbiter to arbitrate the next request on the CEI. The master port state ma-
chine wakes up and requests the SBus whenever there is a request in the
queue. When the whole burst of Data is written to the SBus, the master port
state machine return the acknowledgment (MEMDONE) and status
(CE_DWERR) to the corresponding CE.
When a CE is granted for DMA write, the CEI bus is locked until the whole
burst of write data is moved over to the write data buffer. During this period,
only the slave write operation from the SBus can occur on the CEI. A slave
read would have to wait until the DMA write cycle is done. On the other hand,
a slave read operation will have the same effect as DMA write that will also
lock up the CEI for the duration of the whole transaction.
2.3.1.2 DVMA Read
DVMA Read cycle starts with the highest priority channel engine asserts BR
signal on CEI with RD (bit[63] of CE_DOUT signal) signal asserted. The ar-
biter latches the DVMA address, transfer size and channel ID and places a
Read request into the request command queue of the SBus master port state