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STP2002QFP
Sun Microelectronics
Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP
Note: The receive descriptor pointer must be initialized to a 2K byte-
aligned value after power-on or software reset.
7.5.21 ERX Receive Data Buffer Pointer
This 28-bit loadable counter keeps track of the next DVMA write burst ad-
dress. The counter increments by 1, 2, or 4 (depending on the burst size) after
a DVMA write burst cycle has been executed by the receive DMA engine.
The counter is loaded with the Free_Buffer_Pointer during the descriptor
fetch phase. This counter is used to generate the DVMA write burst address.
7.5.22 ERX RxFIFO Write Pointer
This 9-bit loadable counter points to the next location in the RxFIFO that will
be loaded with data from the RX_MAC. The counter increments by 1 or 2
(depending on SBus configuration) after a word (or double-word) was loaded
into the FIFO. The counter is loaded with the contents of Shadow Write
Pointer, when an “early receive abort” needs to be performed. This counter
generates the “write” address for the RxFIFO memory core.
Table 126: ERX Receive Descriptor Pointer Register Definition
Field Bits Description Type
28:8 Base address for the descriptor ring R/W
7:0 Displacement for the current descriptor R/W
Table 127: ERX Receive Data Buffer Pointer Register Address
Register Physical Address Access Size
ERX Receive Data Buffer Pointer register 0x8C0_4008 4 bytes
Table 128: ERX Receive Data Buffer Pointer Register Definition
Field Bits Description Type
27:0 Counter, keeps track of next DVMA write
burst address
R