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STP2002QFP
Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP
Sun Microsystems,
IDLE:
When this bit is set, it indicates that the parallel port data transfer state ma-
chines are in their idle states. The state machines should be idle when chang-
ing direction and/or configuring operational modes and when enabling a
memory clear operation.
SRST:
Setting this bit will place the parallel port data transfer state machines and
programmable timers into reset. It will not reset any of the parallel port reg-
Table 29: Operation Configuration Register Address
Register Physical Address Access Size
Operation configuration register (P_HCR) 0xC80_0012 2 bytes
Table 30: Operation Configuration Register Definition
Field Bits Description Type
0 Reserved R/W
1 Reserved R
2 Reserved R
IDLE 3 Reads as 1, when the PP data transfer state machines
are idle
R
4 Reserved R
5 Reserved R
6 Reserved R
SRST 7 When set, resets the parallel port. Must be reset by
software.
R/W
ACK_OP 8 Acknowledge operation R/W
BUSY_OP 9 Busy operation R/W
EN_DIAG 10 When set, enables diagnostic operation R/W
ACK_DSEL 11 Acknowledge bidirectional select. When set,
P_BSY is bidirectional
R/W
BUSY_DSEL 12 Busy bidirectional select. When set, P_D_STRB is
bidirectional
R/W
DS_SEL 13 Data strobe bidirectional select. When set,
P_D_STRB is bidirectional
R/W
DATA_SRC 14 Data source for memory clear operation R/W
MEM_CLR 15 When set, enables memory clear R/W