Filter
Top Products
132
STP2002QFP
Sun Microelectronics
Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP
7.5.70 MIF Bit-Bang Clock
This one-bit register is used to generate the MDC clock waveform on the MII
management interface when the MIF is programmed in the Bit-Bang Mode.
Writing a 1 after a 0 into this register will create a rising edge on the MDC,
while writing a 0 after a 1 will create a falling edge. For every bit that is trans-
ferred on the management interface, both edges have to be generated.
7.5.71 MIF Bit-Bang Data
This one-bit register is used to generate the outgoing data (MDO) on the MII
management interface when the MIF is programmed in the Bit-Bang Mode.
The data will be steered to the appropriate MDIO based on the state of the
PHY_Select bit in the MIF configuration register.
7.5.72 MIF Bit-Bang Output Enable
This one-bit register is used to enable (1) and disable (0) the I-directional
driver on the MII management interface when the MIF is programmed in the
Bit-Bang Mode. The MDIO should be enabled when data bits are transferred
from the MIF to the transceiver, and it should be disabled when the interface
is idle or when data bits are transferred from the transceiver to the MIF (data
portion of a read instruction). Only one MDIO will be enabled at a given time,
depending on the state of the PHY_Select bit in the MIF configuration regis-
ter.
Table 221: RX_MAC Address Filter Mask Register Definition
Field Bits Description Type
11:0 Contains 12 bit nibble mask for the Address Filter. R/W
Table 222: MIF Bit-Bang Clock Address
Register Physical Address Access Size
MIF bit-bang clock 0x8C0_7000 4 bytes
Table 223: MIF Bit-Bang Data Address
Register Physical Address Access Size
MIF bit-bang data 0x8C0_7004 4 bytes