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STP2002QFP
Sun Microelectronics
Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP
7.2.2 DMA Address and Next Address Register
This 32-bit read/write register contains the virtual address for parallel port
DMA transfers. It is implemented as a 32-bit loadable counter which points
to the next byte that will be accessed via the parallel port.
If the P_EN_NEXT (enable next address) bit in the P_CSR is set, then a
write to the P_ADDR register will write to the P_NEXT_ADDR register
instead. If P_EN_NEXT is set when the byte counter (P_BCNT) expires, and
the P_NEXT_ADDR register has been written since the last time the byte
counter expired, then the contents of P_NEXT_ADDR are copied into
P_ADDR. If P_EN_NEXT is set when the byte counter (P_BCNT) expires,
but the P_NEXT_ADDR register has not been written since the last time the
byte counter expired, then DMA activity is stopped and DMA requests from
the parallel port will be ignored until P_NEXT_ADDR is written or
P_EN_NEXT is cleared. (Also, the P_DMA_ON bit will read as 0 while
DMA is stopped because of this.) When DMA is re-enabled by writing to the
P_NEXT_ADDR register, the contents of P_NEXT_ADDR are copied into
P_ADDR before DMA activity actually begins.
Note: A write to the P_ADDR register will invalidate the P_FIFO. A
write to the P_NEXT_ADDR register does not have this effect.
Table 21: DMA Address and Next Address Register Address
Register Physical Address Access Size
DMA address and next address register (P_ADDR) 0xC80_0004 4 bytes
Table 22: DMA Address and Next Address Register Definition
Field Bits Description Type
P_ADDR 31:0 DVMA address register R/W
P_NEXT_ADDR 31:0 Next DVMA address register W