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STP2002QFP
Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP
Sun Microsystems,
Figure 18.
6.2.4 Bypass Register
The bypass register provides a minimum length path between the test data in-
put and the test data output. It consists of a single shift-register stage that
loads a constant 0 in the Capture-DR TAP controller state when the manda-
tory BYPASS instruction is selected.
Figure 19.
MUX
TDI
ATPG_MODE
BSCAN_CDR
ISCAN_CLK
IR_CLOCK
DR_CLOCK
DR_CLOCK
DR_CLOCK
Boundary Scan Register
Internal Scan Register
JTAG Instruction Register
JTAG ID Register
Bypass Register
Clock Control Register
MUX
Test Mode Selects
JTAG_TDI
DR_CLOCK
DR_SHIFT
BYPASS_SELEC
T
BYPASS_TDO
JTAG_BYPASS