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STP2002QFP
Sun Microelectronics
Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP
7.5.74 MIF Configuration Register
This 15-bit register controls the operation of the MIF.
REGAD 22:18 REGister ADdress.
When issuing an instruction, this field should be loaded
with the address of the register that is to be read/
written.
When polling for completion, this field is always a don’t
care.
R/W
PHYAD 27:23 PHY ADdress.
When issuing an instruction, this field should be loaded
with the XCVR address.
When polling for completion, this field is always a don’t
care.
R/W
OP 29:28 OPcode.
When issuing an instruction, this field should be loaded
with 01 for a write and with 10 for a read.
When polling for completion, this field is always a don’t
care.
R/W
ST 31:30 STart of frame.
When issuing an instruction, this field should always be
loaded with a 01.
When polling for completion, this field is always a don’t
care.
R/W
Table 227: MIF Configuration Register Address
Register Physical Address Access Size
MIF configuration register 0x8C0_7010 4 bytes
Table 226: MIF Frame/Output Register Definition
Field Bits Description Type