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STP2002QFP
Sun Microelectronics
Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP
TESTABILITY 6
6.1 Introduction
This section describes the features of the JTAG Test Access Port (TAP) and
other testability structures for the FEPS. The JTAG macro which implements
the IEEE Standard 1149.1-1990 provides access to the test structures on the
chip.
The TAP includes the TAP controller state machine, an instruction regis-
ter, a bypass register, a device identification register, and the necessary
decoding logic. The TAP requires five dedicated pads: test data input (TDI),
test data output (TDO), test mode select (TMS), test clock (TCK), and test
reset (TRST).
6.2 JTAG Macro
Figure 14.
ISCAN_MODE
JTAG_TDO_EN
BSCAN_CDR
BSCAN_SDI
BSCAN_SDR
BSCAN_UDR
BSCAN_IMC
BSCAN_OMC
JTAG_TDO
ISCAN_CLK
ISCAN_SDR
SCSI_SELECT
ISCAN_SDI
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TRST
BSCAN_TDO
ISCAN_SO
JTAG_CONTR