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STP2002QFP
Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP
Sun Microsystems,
PP_ACKDIR0 1
BUSY_DSEL:
This bit is a bidirectional select for the PP_BSY signal. When reset, PP_BSY
is fixed as an input. When set, PP_BSY is a bidirectional signal. The
PP_BSYDIR pin will reflect the direction of PP_BSY. The switching of di-
rection is controlled by the DIR bit of the transfer control register. The func-
tion of the two pins is as follows:
DIR=0 DIR=1
PP_BSY Input Output
PP_BSYDIR0 1
DS_DSEL:
This bit is a bidirectional select for the PP_STB signal. When reset, PP_STB
is fixed as an output. When set, PP_STB is a bidirectional signal. The
PP_DSDIR pin will reflect the direction of PP_STB. The switching of direc-
tion is controlled by the DIR bit of the transfer control register. The function
of the two pins is as follows:
DIR=0 DIR=1
PP_STB Output Input
PP_DSDIR 1 0
This bit also defines transfer protocol as follows:
1 = Data strobe is bidirectional. Master write transfer protocol is selected.
0 = Data strobe is fixed as an output. Master read/write transfer protocol is
selected.
DATA_SRC:
This bit specifies the data to be sourced during a memory clear operation.
When set, the sourced data will be ones. When reset, the sourced data will be
0s.
MEM_CLR:
This bit enables memory clear operation. The DMA control registers need to
be configured, the DIR bit in the TCR register must be set and DMA must be
enabled.