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STP2002QFP
Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP
Sun Microsystems,
DMA direction. The state of the DIR bit is reflected in the P_WRITE bit of
the P_CSR. Reset state of this bit is 1.
7.2.9 Output Register
The output register is an 8-bit read/write register whose contents are driven
on to the corresponding external pins. In diagnostic mode (EN_DIAG=1),
bits 0–2 are gated on to input register bits 0–2. The external outputs remain
low while diagnostic mode is enabled. All bits are 0 after reset.
7.2.10 Input Register
The input register is an 8-bit read/write register whose contents reflect the
state of several external input pins and their corresponding interrupts. In di-
agnostic mode (EN_DIAG=1), bits 0–2 are driven from output register bits
0–2.
Table 35: Output Register Address
Register Physical Address Access Size
Output register (P_OR) 0xC80_0016 1 byte
Table 36: Output Register Definition
Field Bits Description Type
SLCT_IN 0 Select in. This bit is output on the PP_SLCT_IN pin. R/W
AFXN 1 Auto feed. This bit is output on the PP_AFXN pin. R/W
INIT 2 Initialize. This bit is output on the P_INIT pin R/W
3 Reserved (V1 bit on HIOD parallel port) R/W
4 Reserved (V2 bit on HIOD parallel port) R/W
5 Reserved (V3 bit on HIOD parallel port) R/W
6 Unused (reads as 0) R
7 Unused (reads as 0) R
Table 37: Input Register Address
Register Physical Address Access Size
Input register (P_IR) 0xC80_0017 1 byte