Filter
Top Products
60
STP2002QFP
Sun Microelectronics
Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP
P_DRAINING bits are not valid while P_ERR_PEND is set and should be ig-
nored.
P_INVALIDATE:
Setting this bit invalidates the P_FIFO. If P_ERR_PEND = 0 when
P_INVALIDATE is set, all dirty data in the P_FIFO will first be drained to
memory. If P_ERR_PEND = 1 when P_INVALIDATE is set, all dirty data
in the P_FIFO will be discarded. In addition to invalidating the P_FIFO, set-
ting this bit causes P_ERR_PEND and P_TC to be reset. If P_EN_NEXT =
1, P_A_LOADED, and P_NA_LOADED will also be reset.
P_RESET:
This bit functions as a hardware reset to the parallel port. It will remain active
once written to one until written to zero, unless cleared by an SBus reset
(SB_RESET asserted). Setting P_RESET or asserting SB_RESET will inval-
idate the P_FIFO and reset all parallel port interface state machines to their
idle states. If P_ERR_PEND = 0 when P_RESET is set, all dirty data in the
P_FIFO will first be drained to memory. When this occurs, P_RESET must
not be cleared until draining is complete, as indicated by P_DRAINING = 00.
If P_ERR_PEND = 1 when P_RESET is set, no draining will take place and
all dirty data in the P_FIFO will be discarded.
P_WRITE:
This read only bit reflects the direction for DMA transfers. It is a logical OR
of the DIR bit of the parallel control register (P_TCR) and the MEM_CLR bit
of the parallel operation control register (P_OCR).
P_EN_DMA:
When set, enables DMA transfer to/from parallel port. Loss of data may occur
when DMA is disabled in the middle of a data transfer from parallel port.
P_TC:
This bit will be set when the byte counter (P_BCNT) transitions to/from
0x000001 to 0x000000. This will generate an interrupt if enabled by
P_INT_EN and not disabled by P_TCI_DIS. During unchained transfers,
P_TC causes P_DMA_ON to be reset. When P_EN_NEXT = 0, P_TC is
cleared by P_INVALIDATE, P_RESET, or SB_RESET. When
P_EN_NEXT = 1, P_TC can also be cleared by writing a 1 to it.