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STP2002QFP
Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP
Sun Microsystems,
7.4.12 FAS366 Synchronous Transfer Period Register
The synchronous transfer period register is an eight-bit, write-only register.
This register specifies the minimum time, in input clock cycles, between lead-
ing edges of successive REQ or ACK pulses on the SCSI bus during synchro-
nous data transfers.
7.4.13 FAS366 FIFO Flags Register
The FIFO flags register is an eight-bit, read-only register that provides the
user with the option of addressing only one register for FIFO count and se-
quence information.
7.4.14 FAS366 Synchronous Offset Register
The synchronous offset register is an eight-bit, write-only register. This reg-
ister specifies the maximum REQ/ACK offset allowed during synchronous
transfers. An offset of 0 specifies asynchronous operation.
Table 72: FAS366 Synchronous Transfer Period Register Address
Register Physical Address Access Size
Synchronous transfer period register 0x881_0018 1 byte
Table 73: FAS366 Synchronous Transfer Period Register Definition
Field Bits Description Type
Synchronous transfer
period
7:0 Specifies the time between successive REQ
and ACK pulses on the SCSI bus
W
Table 74: FAS366 FIFO Flags Register Address
Register Physical Address Access Size
FIFO flags register 0x881_001C 1 byte
Table 75: FAS366 FIFO Flags Register Definition
Field Bits Description Type
FIFO flags 7:0 Provides information on FIFO R