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STP2002QFP
Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP
Sun Microsystems,
7.4 FAS366 (SCSI Controller Core) Registers
The FAS366 registers are used by the CPU to control the operation of the
SCSI bus. Through these registers, the CPU configures, commands, and mon-
itors data, command, and information transfers between the FAS366 and the
SCSI bus.
Note: For the case of SCSI read (data-in phase only) when FAS366 is
operating in narrow mode and if the number of bytes coming to
FAS366 from the target is an odd number, FAS366 can be pro-
grammed in two modes.
1) FAS366 does not give up the last one byte. It generates an interrupt
when the last one byte is still in FAS366 FIFO. The device driver has
to make a slave access to FAS366 to write one byte so that the last byte
is padded. Then the device driver can make another slave access to read
both the bytes out and discard the padded byte. This is the default
mode.
2) FAS366 pads the last byte and generates an interrupt only after the
SCSI CE has read all the bytes. This mode can be entered by setting the
bit 7 of the configuration register #3. This bit gets cleared after every
reset.
7.4.1 FAS366 Transfer Counter Low Register (Read Only)
This 16-bit transfer counter register consists of two eight-bit, read-only reg-
isters. The counter is used to count the number of bytes transferred in a DMA
command or received in a command sequence in target mode. When a DMA
command is issued, the transfer counter is loaded with the value contained in
the transfer count register. The value in the transfer counter is decremented as
bytes are transferred.
When a sequence terminates early, the sum of the transfer counter and the
FIFO flags registers indicate the number of bytes remaining to be transferred.
Table 50: FAS366 Transfer Counter Low Register (Read Only) Address
Register Physical Address Access Size
Transfer counter low 0x881_0000 2 bytes