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STP2002QFP
Sun Microelectronics
Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP
7.5.27 ERX RxFIFO
For diagnostic purposes, a PIO path has been provided into the RxFIFO.
When using PIOs, the configuration of the RxFIFO will be 512 × 33bits. In
order to be able to access all the bits in the memory core, the address space of
the RxFIFO has been doubled and split into two apertures as follows:
• Writing to the lower aperture will load 32 bits of data and clear the tag
bit to 0 at the addressed location
• Writing to the higher aperture will load 32 bits of data and set the tag
bit to 1 at the addressed location
• Reading from the lower aperture will return 32 bits of data from the
addressed location
• Reading from the higher aperture will return the tag bit from the
addressed location on data line [0]
Note: The RxFIFO should never be accessed using PIOs during nor-
mal operation.
Table 138: ERX State Machine Register Definition
Field Bits Description Type
4:0 Load control state machine state R
6:5 FIFO pointer state R
9:7 Checksum state machine state R
15:10 Reserved R
19:16 Data state machine state R
23:20 Descriptor state machine state R
25:24 ERX Memdone counter state R
31:26 Reserved R
Table 139: ERX FxFIFO Address
Register Physical Address Access Size
RxFIFO lower aperture
RxFIFO higher aperture
0x8C0_5000 - 0x8C0_57FC
0x8C0_5800 - 0x8C0_5FFC
4 bytes
4 bytes