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STP2002QFP
Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP
Sun Microsystems,
Receive Clock Domain
This clock is used to drive the receive protocol engine in the BigMAC core.
It is sourced by the MII and has the operating frequency of 2.5/25 MHz 100
ppm. The 2.5/25 MHz version of this clock (RX_NCLK) is used for strobing
in the packet data from the MII and for nibble-to-byte conversion of the in-
coming data stream. The 1.25/12.5 MHz divide-by-two version of this clock
(RX_BCLK) is used for receive protocol processing and state machine oper-
ation.
5.2.4 Host Memory Data Management
The device driver maintains two data structures in the host memory: one for
transmit and the other for receive packets. Both data structures are organized
as wrap-around descriptor rings. Each descriptor ring has a programmable
number of descriptors (in the range of 16 through 256). Each descriptor has
two entries (words): a control/status word and a pointer to a data buffer.
The interaction between the hardware and the software is managed via a
semaphore (OWN) bit, that resides in the control/status portion of the descrip-
tor. When the OWN bit is set to 1, the descriptor is owned by the hardware.
If the OWN bit is cleared to 0, the descriptor is owned by the software. The
owner of the descriptor is responsible for releasing the ownership when it can
no longer use it. Once the ownership is released, the previous owner may no
longer treat the descriptor contents as valid, since the new owner may over-
write it at any time.
5.2.5 Transmit Data Descriptor Ring
A transmit packet that is posted by an upper layer protocol to the device driver
may reside in several data buffers (headers and data) which are scattered in
the host memory. When the device driver posts the packet to the hardware, it
allocates a descriptor for each buffer. The descriptor contains the necessary
information about the buffer that the hardware needs for the packet transfer.
When the packet is ready for transmission, the descriptor(s) ownership is
turned over to the hardware, and a programmed I/O command is issued to the
transmit DMA channel to start the packet transfer from the host memory to
the TxFIFO.
When the packet transfer has been completed, the transmit DMA channel
turns over the descriptor ownership back to the driver and polls the next
descriptor in the ring. If the descriptor is owned by the hardware, the next
packet transfer begins. If not, the DMA channel “goes to sleep” until a new
command is issued.