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STP2002QFP
Sun Microelectronics
Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP
7.4.19 FAS366 Configuration #2 Register
Configuration #2 is an eight-bit read/write register that specifies different op-
erating options for the FAS366.
7.4.20 FAS366 Configuration #3 Register
This eight-bit, read/write register is used to enable normal or fast synchronous
transfer timing, ID message reserved bit checking, receipt of three-byte mes-
sages when selected with ATN, and recognition of 10-byte Group 2 com-
mands.
7.4.21 FAS366 Recommand Counter Register
The 16-bit recommand counter consists of two eight-bit, read/write registers:
the recommand counter low register, and the recommand counter high regis-
ter. The recommand counter is enabled when the recommand function is en-
abled, and is disabled when the recommand functions is disabled. The
recommand counter is decremented at the end of each block transfer before
the SCSI command is re-executed.
Table 86: FAS366 Configuration #2 Register Address
Register Physical Address Access Size
Configuration #2 register 0x881_002C 1 byte
Table 87: FAS366 Configuration #2 Register Definition
Field Bits Description Type
Configuration #2 7:0 Specifies different operating options for FAS366 R/W
Table 88: FAS366 Configuration #3 Register Address
Register Physical Address Access Size
Configuration #3 register 0x881_0030 1 byte
Table 89: FAS366 Configuration #3 Register Definition
Field Bits Description Type
Configuration #3 7:0 Specifies different operating options for FAS366 R/W