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STP2002QFP
Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP
Sun Microsystems,
7.5.28 XIF Configuration Register
This 10-bit register determines the parameters that control the operation of
the transceiver interface.
Table 140: XIF Configuration Register Address
Register Physical Address Access Size
XIF configuration register 0x8C0_6000 4 bytes
Table 141: XIF Configuration Register Definition
Field Bits Description Type
Tx_Output_Enable 0 When set to 1, this bit enables the output driv-
ers on the MII transmit bus
R/W
MII_Loopback 1 This mode of operation implements the inter-
nal loopback for the Ethernet channel. The
entire channel is driven off the system clock,
the MII transmit bus is looped back to the MII
receive bus, and the MII Tx_En signal is
looped back to the MII Rx_Dv input
R/W
MII_Buffer_Enable 3 Control and external tristate buffer that may
reside on the MII receive data bus.
R/W
SQE_Test_Enable
(Rev 2.1)
LANCE_Mode
(Rev 2.2)
4 When set to 1, this bit enables the signal qual-
ity error test as defined by IEEE 802.3. This
feature is applicable only if a 10Base-T trans-
ceivers is connected to the MII, that
implements this function.
When set to 1, this bit enables the programma-
ble extension of the Rx-to-Tx IPG. In this
mode, the TxMAC will defer during IPG0 and
IPG1 when timing the Rx-to-Tx IPG, and will
not defer during IPG2. When cleared to 0, the
TxMAC will ignore IPG0, defer during IPG1
when timing Rx-to-Tx IPG, and will not defer
during IPG2.
R/W