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STP2002QFP
Fast Ethernet, Parallel Port, SCSI (FEPS) - STP2002QFP
Sun Microsystems,
*_IRQ_EN: When set, enables interrupts on the corresponding bits of the
input and transfer control registers. Note that the interrupt enable bit of the
PD_SCR must also be enabled to allow a hardware interrupt to be generated.
*_IRP: Defines the polarity of the edge triggered interrupts on the corre-
sponding bits of the input register. 0=interrupt generated on the 1 to 0
transition of the signal. 1= interrupt generated on the 0 to 1 transitions of the
signal. Note that when configuring the interrupt polarity of a given signal, it
is possible to generate a false interrupt. It is suggested that when the interrupt
polarities are being programmed, interrupts be disabled, and all interrupt
sources be cleared upon completion of programming.
ERR_IRQ, SLCT_IRQ, PE_IRQ, BUSY_IRQ:
When set, an interrupt is pending on the corresponding bit. The interrupt is
cleared and the bit is reset when a 1 is written to the corresponding bit. Writ-
Table 40: Interrupt Control Register Definition
Field Bits Description Type
ERR_IRQ_EN 0 When set, enables ERR interrupts R/W
ERR_IRP 1 ERR interrupt polarity. 1=on rising edge, 0=on
trailing edge
R/W
SLCT_IRQ_EN 2 When set, enables SLCT interrupts R/W
SLCT_IRP 3 SLCT interrupt polarity. 1=on rising edge, 0=on
trailing edge
R/W
PE_IRQ_EN 4 When set, enable PE interrupts R/W
PE_IRP 5 PE interrupt polarity. 1=on rising edge, 0=on
trailing edge
R/W
BUSY_IRQ_EN 6 When set, enables BUSY interrupts R/W
BUSY_IRP 7 BUSY interrupt polarity. 1=on rising edge, 0=on
trailing edge
R/W
ACK_IRQ_EN 8 When set, enables ACK interrupts on rising edge
of ACK
R/W
DS_IRQ_EN 9 When set, enables DS interrupts on the rising
edge of DS
R/W
ERR_IRQ 10 When set, error IRQ pending R/W
SLCT_IRQ 11 When set, select IRQ pending R/W
PE_IRQ 12 When set, paper IRQ pending R/W
BUSY_IRQ 13 When set, busy IRQ pending R/W
ACK_IRQ 14 When set, acknowledge IRQ pending R/W
DS_IRQ 15 When set, data strobe IRQ pending R/W