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BIOS POST Checkpoints
BIOS POST Checkpoints E-1
This appendix lists the POST checkpoints of the notebook BIOS.
Table E-1 POST Checkpoint List
Checkpoint Description
04h
• Determines if the current booting procedure is from cold boot (press reset button or
turn the system on), from warm boot (press Ctrl +Alt +Del).
Note: At the beginning of POST, port 64 bit 2 (8042 system flag) is read to determine
whether this POST is caused by a cold or warm boot. If it is a cold boot, a
complete POST is performed. If it is a warm boot, the chip initialization and
memory test is eliminated from the POST routine.
08h
• Disables Non-Maskable Interrupt (NMI), Alarm Interrupt Enable (AIE), Periodical
Interrupt Enable (PIE), and Update-ended Interrupt Enable (UIE).
Note: These interrupts are disabled in order to avoid any mis-action happened during
the POST routine.
09h
• Initializes Intel ChipSet, V3-LS and DRAM type determination(SDRAM or EDO type)
0Ah
• Intel drip GPIO pin initialization and base address assignment
10h
• DMA(8237) testing & initialization
14h
• System timer (8254) testing & initialization
18h
• Memory refresh test; refresh occurrence verification (IRQ0)
1Ch
• Verifies CMOS shutdown byte, battery and check sum
Note: Several parts of the POST routine require the system to be in protected mode.
When returning to real mode from protected mode, the processor is reset,
therefore POST is re-entered. In order to prevent re-initialization of the system,
POST reads the shutdown code stored in location 0Fh in CMOS RAM. Then it
jumps around the initialization procedure to the appropriate entry point.
• The CMOS shutdown byte verification assures that CMOS 0Fh area is fine to execute
POST properly.
• Initializes CMOS default setting
• Initializes RTC time base
Note: The RTC has an embedded oscillator that generates 32.768 KHz frequency. To
initial RTC time base, turn on this oscillator and set a divisor to 32768 so that
RTC can count time correctly.
1Eh
• DRAM sizing
2Ch
• Tests 128K base memory
Note: The 128K base memory area is tested for POST execution. The remaining
memory area is tested later.
20h
• Tests keyboard controller (8041/8042)
• Determines keyboard type (AT, XT, PS/2) then write default command byte upon KB
type