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System Introduction 1-21
1.6.5 GPIO Port Definition Map
Table 1-12 GPIO Port Definition Map I
GPIO/Signal Pin # I/O Description
GPIO Pin Assignment: PIIX4
SUSA# (PX3_SUSA#) W20 O 0: Power down clock generator
GPO0 (PX3_DOCKRST#) G4 O 0 : Enable docking reset
GPO1 (PX3_HDPON) Y15 O 1: Turn on HDD power
GPO2 (PX3_ CD/FDPON) T14 O 1: Turn on CD/FDD power
GPO3 (PX3_ HDRST#) W14 O 0: Reset HDD interface
GPO4 (PX3_CDRST#) U13 O 0: Reset CD interface
GPO5 (PX3_3MODE) V13 O 0: 3 mode drive
GPO6 (PX3_SMBSEL0) Y13 O Select one of three SM buses
GPO7 (PX3_SMBSEL1) T12 O SMBSEL1 SMBSEL0
0 0 DRAM bank 0 SMB
0 1 DRAM bank 1 SMB
1 0 MMO LM75 & clock gen. SMB
1 1 PCMCIA LM75
GPO8 (PX3_DOCKGNT#) T19 O 0: Granted docking
GPO9/GNTA# (PX3_VDPD) N1 O 1: Power down VGA
GPO10/GNTB# (PX3_VGADIS) P2 O 1: Disable VGA from PCI
GPO11/GNTC# (PX3_AUDPON) P4 O 1: Power on analog audio power
GPO12/APICACK# J17 O NC
GPO13/APICCS# H18 O NC
GPO14/IRQ0 (PX3_ROM#) H20 O 0: Enable ROMCS#
GPO15/SUSB# V19 O NC
GPO16/SUSC# U18 O NC
GPO17/CPU_STP#(PX3_CPUSTP#) R1 O 0: Enable CPU clock stop
GPO18/PCI_STP# (PX3_PCISTP#) R2 O 0: Enable PCI clock stop
GPO19/ZZ (PXI_L2ZZ) K16 O 1: Power down L2 cache
GPO20/SUS_STAT1#(PX3_SUSTAT#) T17 O 0: Enable MTXC power down
GPO21/SUS_STAT2#
(PM3_A_ACT/PD#)
T18 O 0: Power down PD6832 Cardbus controller
GPO22/XDIR# (PX3_FDDBEN) M3 O 1: FDD buffer enable
GPO23/XOE# (PX3_SPPD) M4 O 1: Power down serial interface
GPO27 (PX3_SPKOFF) G5 O 1: Turn off speaker
GPO28 (PX3_FLASHVPP) F2 O 1: Enable Flash Vpp control
GPO29 (PX3_FPAGE1) F3 O Force BIOS to high page 1F segment and 3 E
segments
GPO30 (PX3_FPAGE2) F4 O FPAGE2 FPAGE1
0 0 F, E0
0 1 F, E1
1 0 F, E2
1 1 reserved
EXTSMI#(PX3_KRSMIREQ#) V20 O 0: Enable by KBD SMI or RTC wake