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AMD Geode™ SC1200/SC1201 Processor Data Book 285
Core Logic Module - USB Controller Registers - PCIUSB
32579B
Index 14h-2Bh Reserved Reset Value: 00h
Index 2Ch-2Dh Subsystem Vendor ID (RO) Reset Value: 0E11h
Index 2Eh-2Fh Subsystem ID (RO) Reset Value: A0F8h
Index 30h-3Bh Reserved Reset Value: 00h
Index 3Ch Interrupt Line Register (R/W) Reset Value: 00h
This register identifies the system interrupt controllers to which the device’s interrupt pin is connected. The value of this register is used
by device drivers and has no direct meaning to USB.
Index 3Dh Interrupt Pin Register (R/W) Reset Value: 01h
This register selects which interrupt pin the device uses. USB uses INTA# after reset. INTB#, INTC# or INTD# can be selected by writ-
ing 2, 3 or 4, respectively.
Index 3Eh Min. Grant Register (RO) Reset Value: 00h
This register specifies how long a burst is needed by the USB, assuming a clock rate of 33 MHz. The value in this register specifies a
period of time in units of 1/4 microsecond.
Index 3Fh Max. Latency Register (RO) Reset Value: 50h
This register specifies how often (in units of 1/4 microsecond) the USB needs access to the PCI bus assuming a clock rate of 33 MHz.
Index 40h-43h ASIC Test Mode Enable Register (R/W) Reset Value: 000F0000h
Used for internal debug and test purposes only.
Index 44h ASIC Operational Mode Enable Register (R/W) Reset Value: 00h
7:1 Write Only. Read as 0s.
0 Data Buffer Region 16.
0: The size of the region for the data buffer is 32 bytes.
1: The size of the region for the data buffer is 16 bytes.
Index 45h-FFh Reserved Reset Value: 00h
Table 6-41. PCIUSB: USB PCI Configuration Registers (Continued)
Bit Description
Table 6-42. USB_BAR+Memory Offset: USB Controller Registers
Bit Description
Offset 00h-03h HcRevision Register (RO) Reset Value = 00000110h
31:8 Reserved. Read/Write 0s.
7:0 Revision (Read Only). Indicates the Open HCI Specification revision number implemented by the Hardware. USB sup-
ports 1.0 specification. (X.Y = XYh).
Offset 04h-07h HcControl Register (R/W) Reset Value = 00000000h
31:11 Reserved. Read/Write 0s.
10 RemoteWakeupConnectedEnable. If a remote wakeup signal is supported, this bit enables that operation. Since there is
no remote wakeup signal supported, this bit is ignored.
9 RemoteWakeupConnected (Read Only). This bit indicated whether the HC supports a remote wakeup signal. This imple-
mentation does not support any such signal. The bit is hard-coded to 0.
8 InterruptRouting. This bit is used for interrupt routing:
0: Interrupts routed to normal interrupt mechanism (INT).
1: Interrupts routed to SMI.