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330 AMD Geode™ SC1200/SC1201 Processor Data Book
Video Processor Module
32579B
Flicker Filter, Progressive Video and
YUV or RGB Mixing/Blending
If RGB mixing/blending is enabled, then the flicker filter’s ½,
1, ½ coefficients in the Mixer/Blender block can not be
used. If progressive video is mixed/blended the ½, 1, ½
coefficients can not be used because the video will be dis-
torted. Therefore the ¼, ½, ¼ coefficients must be used.
This setting of the flicker filter effects both the video and the
graphics data. This setting is not a recommended setting
but it is the only choice, other than disabling the flicker filter,
if simultaneous TV and CRT/TFT output is desired.
Flicker Filter, Interlaced Video and
RGB Mixing/Blending
Flicker filter should not be enabled. Neither flicker filter
choice results in an acceptable image.
Scan Rate Conversion
After the flicker filter, the image is scan rate converted from
progressive to interlace. This is the scan protocol needed
for TV. The image also crosses a clock domain. Up to this
point the image has been in the GX1 module’s graphics
clock domain. With the line buffer it moves into the TVOUT
block’s timing generator clock domain.
7.2.4.2 Pre-Encoder Horizontal Scaler
The image can now be upscaled or downscaled horizon-
tally. F4FAR0+Memory Offset 810h[30:24] and
F4FAR0+Memory Offset 814h[10] controls the pre-encoder
horizontal scaler.
7.2.4.3 Video Output Port (VOP)
The image is VESA Video Interface Port Rev. 1.1 Task B
encoded and sent to the VOP interface. The encoded data
only contains active video. It does not contain an ancillary
data block, sliced VBI data, or audio data. The VOP inter-
face is enabled through the pin multiplexing registers of the
General Configuration Block (see Section 4.2 "Pin Multi-
plexing, Interrupt Selection, and Base Address Registers"
on page 72).
7.2.4.4 TV Encoder Timing Generator
The timing generator generates all the necessary clocks to
properly drive an NTSC TV or PAL TV and the Video Out-
put Port.
7.2.4.5 TV Encoder
This block creates the TV signals. Both NTSC and PAL
encodings are supported. F4FAR0+Memory Offset C00h-
C14h program the TV encoder.
Closed captioning information can be output to the TV
under direct program control. F4FAR0+Memory Offset
818h-828h stores, controls, and positions the closed cap-
tioning information.
7.2.5 VESA DDSC2B and DPMS Support
The Video Processor supports VESA, DDSC2B, and
DPMS standards for enhanced monitor communications
and power management support. This support is provided
via signals DDC_SCL (muxed with IDE_DATA10) and
DDC_SDA (muxed with IDE_DATA9). F4BAR0+Memory
Offset 04h[24, 23, 22] controls the interface.
7.2.6 Integrated DACs
The Video Processor uses a Digital to Analog Converter
(DAC) for CRT and TV.
To interface directly with the CRT display, the Video Pro-
cessor incorporates triple 8-bit video DACs. The integrated
DACs drive the RED, GREEN and BLUE inputs of the CRT.
Each integrated DAC is an 8-bit current output type which
can run at a clock rate of up to 135 MHz. The integrated
DAC can generate voltage levels from 0 to 1.0V, when driv-
ing 75 Ω double-terminated loads.
Differential and integral linearity errors, over full tempera-
ture and voltage ranges, are less than one LSB.
The peak white voltage (V
FR
- full range output voltage),
generated at the DAC, is defined according to the following
formula:
V
FR
= 3.35(V
REF
/ R
SET
)
*
75
where:
V
REF
is the voltage at VREF (either internal bandgap refer-
ence, or externally connected voltage reference).
R
SET
is the value of resistance between SETRES and
AV
SS
(typically 470 Ω).
Figure 7-14. DAC Voltage Levels
DAC
AV
SS
CRT
R
L
R
L
Monitor