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394 AMD Geode™ SC1200/SC1201 Processor Data Book
Electrical Specifications
32579B
9.3.7 Sub-ISA Interface
All output timing is guaranteed for 50 pF load, unless otherwise specified. The ISA Clock divisor (defined in F0 Index
50h[2:0] of the Core Logic module) is 011.
Table 9-24. Sub-ISA Timing Parameters
Symbol Parameter
Bus
Width
(Bits) Type
Min
(ns)
Max
(ns) Figure Comments
t
RD1
MEMR#/DOCR#/RD#/TRDE# read
active pulse width FE to RE
16 M 225 9-20 Standard
t
RD2
MEMR#/DOCR#/RD#/TRDE# read
active pulse width FE to RE
16 M 105 9-20 Zero wait state
t
RD3
IOR#/RD#/TRDE# read active pulse
width FE to RE
16 I/O 160 9-20 Standard
t
RD4
IOR#/MEMR#/DOCR#/RD#/TRDE#
read active pulse width FE to RE
8 M, I/O 520 9-20 Standard
t
RD5
IOR#/MEMR#/DOCR#/RD#/TRDE#
read active pulse width FE to RE
8 M, I/O 160 9-20 Zero wait state
t
RCU1
MEMR#/DOCR#/RD#/TRDE#
inactive pulse width
16 M 103 9-20
t
RCU2
MEMR#/DOCR#/RD#/TRDE#
inactive pulse width
8M163 9-20
t
RCU3
IOR#/RD#/TRDE# inactive pulse
width
8, 16 I/O 163 9-20
t
WR1
MEMW#/WR# write active pulse
width FE to RE
16 M 225 9-21 Standard
t
WR2
MEMW#/DOCW#/WR# write active
pulse width FE to RE
16 M 105 9-21 Zero wait state
t
WR3
IOW#/WR# write active pulse width
FE to RE
16 I/O 160 9-21 Standard
t
WR4
IOW#/MEMW#/DOCW#/WR# write
active pulse width FE to RE
8 M, I/O 520 9-21 Standard
t
WR5
IOW#/MEMW#/DOCW#/WR# write
active pulse width FE to RE
8 M, I/O 160 9-21 Zero wait state
t
WCU1
MEMW#/WR#/DOCW# inactive pulse
width
16 M 103 9-21
t
WCU2
MEMW#/WR#/DOCW# inactive pulse
width
8M163 9-21
t
WCU3
IOW#/WR# inactive pulse width 8, 16 I/O 163 9-21
t
RDYH
IOR#/MEMR#/RD#/DOCR#/IOW#/
MEMW#/WR#/DOCW# hold after
IOCHRDY RE
8, 16 M, I/O 120 9-20
9-21
t
RDYA1
IOCHRDY valid after IOR#/MEMR#/
RD#/DOCR#/IOW#/MEMW#/WR#/
DOCW# FE
16 M, I/O 78 9-20
9-21