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Introduction
ARM DUI 0125A
© Copyright ARM Limited 1999. All rights reserved.
1-5
1.2.2 Core module FPGA
The FPGA provides system control functions for the core module, enabling it to operate
as a standalone development system or attached to a motherboard. These functions are
outlined in this section and described in detail in Chapter 3 Hardware Description.
SDRAM controller
The SDRAM controller is implemented within the FPGA. This provides support for
Dual In-line Memory Modules (DIMMs) with a capacity of between 16 and 256MB.
See SDRAM controller on page 3-6.
Reset controller
The reset controller initializes the core and allows the core module to be reset from five
sources:
• reset button
• motherboard
• other core modules
• Multi-ICE
• software.
For information about the reset controller, see Reset controller on page 3-8.
System bus bridge
The system bus bridge provides an interface between the memory bus on the core
module and the system bus on a motherboard. It allows the local processor access to
interface resources on the motherboard and to the SDRAM on other core modules. It
also allows access to the local SDRAM from the PCI bridge on the motherboard and
processors on other core modules (see System bus bridge on page 3-11).