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Hardware Description
3-16
© Copyright ARM Limited 1999. All rights reserved.
ARM DUI 0125A
The example in Figure 3-8 illustrates how a group of four signals (labelled A, B, C, and
D) are routed through a group of four connector pins up through the stack. It highlights
how signal C is rotated as it passes up through the stack and only utilized on module 2.
All four signals are rotated and utilized in a similar way, as follows:
• signal A on core module 0
• signal B on core module 1
• signal C used on core module 2
• signal D used on core module 3.
For details of the signals on the HDRB connectors, see HDRB on page A-4.
Note
The JTAG signals are discussed in Multi-ICE support on page 3-21.
3.6.5 Bus operating modes
The bus operating modes are programmed by writing to coprocessor 15 register 1 within
the ARM940T microprocessor core.
The Integrator system supports:
• asynchronous and FastBus clocking
• little-endian addressing.
The Integrator system does not support:
• synchronous clocking
• big-endian addressing.
For details of how to set the bus operating parameters, refer to the ARM940T Technical
Reference Manual.