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© Copyright ARM Limited 1999. All rights reserved.
ARM DUI 0125A
3.5 Reset controller ............................................................................................ 3-8
3.6 System bus bridge...................................................................................... 3-11
3.7 Clock generators ........................................................................................ 3-17
3.8 Multi-ICE support........................................................................................ 3-21
Chapter 4 Programmer’s Reference
4.1 Memory organization.................................................................................... 4-2
4.2 Exception vector mapping............................................................................ 4-6
4.3 Core module registers .................................................................................. 4-7
4.4 Interrupt registers ....................................................................................... 4-19
Appendix A Signal Descriptions
A.1 HDRA ...........................................................................................................A-2
A.2 HDRB ...........................................................................................................A-4
Appendix B Specifications
B.1 Electrical specification ..................................................................................B-2
B.2 Timing specification......................................................................................B-3
B.3 Mechanical details........................................................................................B-4