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4-16
© Copyright ARM Limited 1999. All rights reserved.
ARM DUI 0125A
4.3.8 CM_SPD (0x10000100 to 0x100001FC)
This area of memory contains a copy of the SPD data from the SPD EEPROM on the
DIMM. Because accesses to the EEPROM are very slow, the data is copied to this
memory during board initialization to allow faster random access to the SPD data (see
Serial presence detect on page 3-6). The SPD memory contains 256 bytes of data, the
most important of which are as shown in Table 4-9.
Check for valid SPD data as follows:
1. Add together all bytes 0 to 62.
2. Logically AND the result with 0xFF.
3. Compare the result with byte 63.
If the two values match, then the SPD data is valid.
Note
A number of SDRAM DIMMs do not comply with the JEDEC standard and do not
implement the checksum byte. The Integrator is not guaranteed to operate with
non-compliant DIMMs.
The code segment shown in Example 4-1 on page 4-17 can be used to correctly setup
and remap the SDRAM.
Table 4-9 SPD memory contents
Byte Contents
2 Memory type
3 Number of row addresses
4 Number of column addresses
5 Number of banks
31 Module bank density (MB
divided by 4)
18 CAS latencies supported
63 Checksum
64:71 Manufacturer
73:90 Module part number