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Hardware Description
3-6
© Copyright ARM Limited 1999. All rights reserved.
ARM DUI 0125A
3.4 SDRAM controller
The core module provides support for a single 16, 32, 64, 128, or 256MB SDRAM
DIMM.
3.4.1 SDRAM operating mode
The operating mode of the SDRAM devices is controlled with the mode set register
within each SDRAM. These registers are set immediately after power-up to specify:
• a burst size of four for both reads and writes
• Column Address Strobe (CAS) latency of 2 cycles.
The CAS latency and memory size can be reprogrammed via the SDRAM control
register (CM_SDRAM) at address 0x10000020. See CM_SDRAM (0x10000020) on
page 4-14.
Note
Before the SDRAM is used it is necessary to read the SPD memory and program the
CM_SDRAM register with the parameters indicated in Table 4-8 on page 4-14. If these
values are not correctly set then SDRAM accesses may be slow or unreliable.
3.4.2 Access arbitration
The SDRAM controller provides two ports to support reads and writes by the local
processor core and by masters on the motherboard. The SDRAM controller uses an
alternating priority scheme to ensure that the processor core and motherboard have
equal access (see System bus bridge on page 3-11).
3.4.3 Serial presence detect
JEDEC-compliant SDRAM DIMMs incorporate a Serial Presence Detect (SPD)
feature. This comprises a 2048-bit serial EEPROM located on the DIMM with the first
128 bytes programmed by the DIMM manufacturer to identify the following:
• module type
• memory organization
• timing parameters.
The EEPROM clock (SCL) operates at 93.75kHz (24MHz divided by 256). The transfer
rate for read accesses to the EEPROM is 100kbit/s maximum. The data is read out
serially 8 bits at a time, preceded by a start bit and followed by a stop bit. This makes
reading the EEPROM a very slow process because it takes approximately 27ms to read
all 256 bytes. However, during power-up the contents of the EEPROM are copied into