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ARM DUI 0125A
© Copyright ARM Limited 1999. All rights reserved.
4-21
4.4.4 CM_IRQ_ENCLR(0x1000004C)/CM_FIQ_ENCLR (0x1000006C)
The clear set locations are used to set bits in the enable register as follows:
• clear bits in the enable register by writing to the ENCLR location for the
required IRQ or FIQ controller:
1 = CLEAR the bit.
0 = leave the bit unchanged.
4.4.5 Interrupt register bit assignment
The bit assignments for the IRQ and FIQ status, raw status and enable register are
shown in Table 4-11.
Table 4-11 IRQ and FIQ register bit assignment
Bit Name Function
2 COMMTx Debug communications transmit interrupt.
This interrupt indicates that the communications channel is
available for the processor to pass messages to the debugger.
1 COMMRx Debug communications receive interrupt.
This interrupt indicates to the processor that messages are
available for the processor to read.
0 SOFT Software interrupt