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Hardware Description
ARM DUI 0125A
© Copyright ARM Limited 1999. All rights reserved.
3-23
3.8.2 Debugging modes
The core module is capable of operating in two modes:
• normal debug mode
• configuration mode.
Normal debug mode
During normal operation and software development, the core module operates in debug
mode. The debug mode is selected by default (when a jumper is not fitted at the
CONFIG link, see Figure 3-10 on page 3-21). In this mode, the processor core and
debuggable devices on other modules are accessible on the scan chain, as shown in
Figure 3-11 on page 3-22.
Configuration mode
In configuration mode the debuggable devices are still accessible and, in addition, all
FPGAs and PLDs in the system are added into the scan chain. This allows the board to
be configured or upgraded in the field using Multi-ICE or other JTAG debugging
equipment.
To select configuration mode, fit a jumper to the CONFIG link on the core module at
the top of the stack (see Figure 3-10 on page 3-21). This has the effect of pulling the
nCFGEN signal LOW which illuminates the CFG LED (yellow) on each module in the
stack and reroutes the JTAG scan path. The LED provides a warning that the
development system is in the configuration mode.
Note
Configuration mode is guaranteed for a single core module attached to a motherboard
but may be unreliable if more than one core module is attached. The larger loads on the
TCK and TMS lines may cause unreliable operation.
After configuration or code updates you must:
1. Remove the CONFIG link.
2. Power cycle the development system.