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4-10
© Copyright ARM Limited 1999. All rights reserved.
ARM DUI 0125A
11 Reserved Use read-modify-write to preserve value.
10:8 COREOD Read/write Core clock output divider:
000 = divide by 10
001 = divide by 2 (default)
010 = divide by 8
011 = divide by 4
100 = divide by 5
101 = divide by 7
110 = divide by 9
111 = divide by 6.
7:0 COREVCO Read/write Core clock VCO divider word. Defines the
binary value of the V[7:0] pins of the clock
generator (V[8] is tied low).
00000100 = 12MHz (default with OD = 2).
Table 4-4 CM_OSC register (continued)
Bits Name Access Function