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ARM DUI 0125A
© Copyright ARM Limited 1999. All rights reserved.
3-13
3.6.2 Motherboard accesses to SDRAM
The second FIFO supports read and write accesses by system bus masters on the
motherboard and other core modules to the local core module memory.
System bus writes
The data routing for system bus writes to SDRAM is illustrated in Figure 3-6.
Figure 3-6 System bus writes to SDRAM
Write transactions from the system bus to the SDRAM normally complete in a single
cycle on the system bus. The data, address, and control information associated with the
transfer are posted into the FIFO, and the transfer into the SDRAM completes when the
SDRAM is available. If the FIFO is full, then the system bus master receives a retract
response indicating that the arbiter may grant the bus to another master and that this
transaction must be retried later.
Processor
core
SDRAM
controller
Motherboard
SDRAM
FIFO
FIFO