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Hardware Description
ARM DUI 0125A
© Copyright ARM Limited 1999. All rights reserved.
3-11
3.6 System bus bridge
The system bus bridge provides an asynchronous bus interface between the local system
bus and system bus connecting the motherboard and other modules.
Inter-module accesses are supported by two 16 x 74-bit FIFOs. Each of the 16 entries
in the FIFOs contains:
• 32-bit data used for write transfers
• 32-bit address used for reads and writes
• 10-bit transaction control used for reads and writes.
3.6.1 Processor accesses to the system bus
The first FIFO supports read and write accesses by the local processor to the system bus,
which extends onto the motherboard and other modules.
Processor writes
The data routing for processor writes to the system bus is illustrated in Figure 3-4.
Figure 3-4 Processor writes to the system bus
Processor
core
SDRAM
controller
Motherboard
SDRAM
FIFO
FIFO