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3-14
© Copyright ARM Limited 1999. All rights reserved.
ARM DUI 0125A
System bus reads
The data routing for system bus reads from SDRAM is illustrated in Figure 3-7.
Figure 3-7 System bus reads from SDRAM
For system bus reads, the address and control information also pass through the FIFO,
but the returned data from the SDRAM bypasses the FIFO.
The order of transactions on the system bus and the memory bus is preserved. Any
previously posted write transactions are drained from the FIFO (that is, writes to
SDRAM are completed) before the read transfer is performed.
3.6.3 Multiprocessor
The two FIFOs operate independently, as described above, and can be accessed at the
same time. This makes it possible for a local processor to read local SDRAM via the
system bus (through both FIFOs). This feature can be used to support multiprocessor
systems that share data in SDRAM because the processors can all access the same
DRAM locations at the same addresses.
Processor
core
SDRAM
controller
Motherboard
SDRAM
FIFO
FIFO