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Hardware Description
3-20
© Copyright ARM Limited 1999. All rights reserved.
ARM DUI 0125A
The LCLK clock signal is buffered by a 5-output low-skew buffer PI49FCT3805 to
drive five loads. These are:
• SDRAM_CLK[3:0]
•SSRAM_CLK.
The nLCLK clock signal is a phase-aligned inversion of the LCLK signal. It is
buffered by a 5-output low-skew buffer PI49FCT3805 to four loads. These are:
• ARM_BCLK_M
•PLD_BCLK_M
• FPGA_BCLK_M
•LA_BCLK_M.
All clocks are series terminated with 33
Ω
resistors placed as close to the source as
possible.
3.7.3 FPGA reference clock (REFCLK)
The REFCLK signal is used by the FPGA to generate the SDRAM refresh clock and
SPD EEPROM clock. This is a fixed-frequency clock of 24MHz which is output from
the reference pin of the second ICS525 chip U7.