Filter
Top Products
Programmer’s Reference
4-22
© Copyright ARM Limited 1999. All rights reserved.
ARM DUI 0125A
4.4.6 CM_SOFT_INTSET (0x10000050)/CM_SOFT_INTCLT (0x10000054)
The core module interrupt controller provides a register for controlling and clearing
software interrupts. This register is accessed using the software interrupt set and
software interrupt clear locations. The set and clear locations are used as follows:
• Set the software interrupt by writing to the CM_SOFT_INTSET location:
1 = SET the software interrupt
0 = leave the software interrupt unchanged.
• Read the current state of the of the software interrupt register from the
CM_SOFT_INTSET location. A bit set to 1 indicates that the corresponding
interrupt request is active.
• Clear the software interrupt by writing to the CM_SOFT_INTCLR location:
1 = CLEAR the software interrupt.
0 = leave the software interrupt unchanged.
The bit assignment for the software interrupt register is shown in Table 4-12.
Note
The software interrupt described in this section is used by software to generate IRQs or
FIQs. It should not be confused with the ARM SWI software interrupt instruction. See
the ARM Architecture Reference Manual.
Table 4-12 IRQ register bit assignment
Bit Name Function
0 SOFT Software interrupt