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Hardware Description
ARM DUI 0125A
© Copyright ARM Limited 1999. All rights reserved.
3-3
3.2 SSRAM controller
The SSRAM controller is implemented in a Xilinx 9572 PLD which enables the
SSRAM to achieve single-cycle operation. In addition to controlling accesses to the
SSRAM, the controller generates the processor response signals (BWAIT, BERROR,
BLAST) for all accesses to:
•SSRAM
•SDRAM
• status and configuration register space
• system bus bridge.