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Hardware Description
ARM DUI 0125A
© Copyright ARM Limited 1999. All rights reserved.
3-9
3.5.1 Reset signals
Table 3-1 describes the external reset signals.
Table 3-1 Reset signal descriptions
Name Description Type Function
BnRES_M Processor reset Output The BnRES_M signal is used to reset the processor core. It is
generated from nSRST LOW when the core module is used
standalone, or nSYSRST LOW when the core module is
attached to a motherboard.
It is asserted as soon as the appropriate input becomes active.
It is deasserted synchronously from the falling edge of the
processor bus clock.
nDONE FPGA configured Input The nDONE signal is an inversion of the open collector
signal FPGADONE which is generated by all FPGAs when
they have completed their configuration. The FPGADONE
signal is routed round the system through the HDRB
connectors to the inputs of all other FPGAs in the system. The
signal nSRST is held asserted until nDONE is driven LOW.
nMBDET Motherboard detect Input The nMBDET signal is pulled LOW when the core module is
attached to a motherboard and HIGH when the core module is
used standalone.
When MBDET is LOW, nSYSRST is used to generate the
BnRES_M signal.
When nMBDET is HIGH, nSRST is used to generate the
BnRES_M signal.
PBRST Push-button reset Input The PBRST signal is generated by pressing the reset button.
nSRST System reset Bidirectional The nSRST open collector output signal is driven LOW by
the core module FPGA when the signal PBRST or software
reset (SWRST) is asserted.
As an input, nSRST can be driven LOW by Multi-ICE.
If there is no motherboard present, the nSRST signal is
synchronized to the processor bus clock to generate the
BnRES-M signal.
nSYSRST System reset Input The nSYSRST signal is generated by the system controller
FPGA on the motherboard. It is used to generate the
BnRES_M signal when the core module is attached to a
motherboard. It is selected by the motherboard detect signal
(nMBDET).