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Hardware Description
ARM DUI 0125A
© Copyright ARM Limited 1999. All rights reserved.
3-27
3.8.4 Debug communications interrupts
The ARM940T processor core incorporates EmbeddedICE hardware and provides a
debug communications data register which is used to pass data between the processor
and JTAG equipment. The processor accesses this register as a normal 32-bit read/write
register and the JTAG equipment reads and writes the register using the scan chain. For
a description of the debug communications channel, see the ARM940T Technical
Reference Manual.
Interrupts can be used to signal when data has been written into one side of the register
and is available for reading from the other side. These interrupts are supported by the
interrupt controller within the core module FPGA and can be enabled and cleared by
accessing the interrupt registers (see Interrupt registers on page 4-19).