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ARM DUI 0125A
© Copyright ARM Limited 1999. All rights reserved.
4-19
4.4 Interrupt registers
The core module provides a 3-bit IRQ controller and 3-bit FIQ controller to support the
debug communications channel used for passing information between applications
software and the debugger. The interrupt control registers are listed in Table 4-10.
The IRQ and FIQ controllers each provide three registers for controlling and handling
interrupts. These are:
• status register
• raw status register
• enable register, which is accessed using the enable set and enable clear locations.
The way that the interrupt enable, clear, and status bits function for each interrupt is
illustrated in Figure 4-4 on page 4-20 and described in the following subsections. The
illustration shows the control for one IRQ bit. The remaining IRQ bits and FIQ bits are
controlled in a similar way.
Table 4-10 Interrupt controller registers
Register Name Address Access Size Description
CM_IRQ_STAT 0x10000040 Read 3 bits Core module IRQ status register
CM_IRQ_RSTAT 0x10000044 Read 3 bits Core module IRQ raw status register
CM_IRQ_ENSET 0x10000048 Read/write 3 bits Core module IRQ enable set register
CM_IRQ_ENCLR 0x1000004C Write 3 bits Core module IRQ enable clear register
CM_SOFT_INTSET 0x10000050 Read/write 1 bit Core module software interrupt set
CM_SOFT_INTCLR 0x10000054 Write 1 bit Core module software interrupt clear
CM_FIQ_STAT 0x10000060 Read 3 bits Core module FIQ status register
CM_FIQ_RSTAT 0x10000064 Read 3 bits Core module FIQ raw status register
CM_FIQ_ENSET 0x10000068 Read/write 3 bits Core module FIQ enable set register
CM_FIQ_ENCLR 0x1000006C Write 3 bits Core module FIR enable clear register