ARM R4F Computer Hardware User Manual


 
Level One Memory System
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-7
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8.3 Fault handling
Faults can occur on instruction fetches for the following reasons:
MPU background fault
MPU permission fault
External AXI slave error (SLVERR)
External AXI decode error (DECERR)
Cache parity or ECC error
TCM parity or ECC error
TCM external error
TCM external retry request
Breakpoints, and vector capture events.
Faults can occur on data accesses for the following reasons:
MPU background fault
MPU permission fault
MPU alignment fault
External AXI slave error (SLVERR)
External AXI decode error (DECERR)
Cache parity or ECC error
TCM parity or ECC error
TCM external error
TCM external retry request
Watchpoints.
Fault handling is described in:
Faults
Fault status information on page 8-9
Correctable Fault Location Register on page 8-10
Usage models on page 8-10.
8.3.1 Faults
The classes of fault that can occur are:
MPU faults
External faults on page 8-8
Cache and TCM parity and ECC errors on page 8-8
TCM external faults on page 8-8
Debug events on page 8-9.
MPU faults
The MPU can generate an abort for various reasons. See MPU faults on page 7-12 for more
details. MPU faults are always precise, and take priority over other types of abort. If an MPU
fault occurs on an access that is not in the TCM, and is Non-cacheable, or has generated a
cache-miss, the AXI transactions for that access is not performed.